library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tb_alu is
end tb_alu;

architecture BEH of tb_alu is
    component alu
        Port ( a : in  STD_LOGIC_VECTOR(7 downto 0);
               b : in  STD_LOGIC_VECTOR(7 downto 0);
               ci : in std_logic;
               op : in  STD_LOGIC_VECTOR(1 downto 0);
               f : out  STD_LOGIC_VECTOR(7 downto 0);
               c : out  STD_LOGIC;
               z : out  STD_LOGIC;
               s : out  STD_LOGIC;
               mov : in  STD_LOGIC );
    end component;

    signal a, b, f : STD_LOGIC_VECTOR(7 downto 0);
    signal ci : std_logic;
    signal op : STD_LOGIC_VECTOR(1 downto 0);
    signal c, z, s, mov : STD_LOGIC;

begin
    uut: alu
        Port map ( a => a,
                   b => b,
                   ci => ci,
                   op => op,
                   f => f,
                   c => c,
                   z => z,
                   s => s,
                   mov => mov
                   );

    process
    begin
        -- Test 1: A + B
        mov <= '0';
        a <= "00000001";
        b <= "00000001";
        op <= "00";
        ci <= '0';
        wait for 10 ns;
        assert f = "00000010" and c = '0' and z = '0' and s = '0' report "Test 1 failed";

        -- Test 2: A - B
        a <= "00000010";
        b <= "00000001";
        op <= "01";
        ci <= '0';
        wait for 10 ns;
        assert f = "00000001" and c = '0' and z = '0' and s = '0' report "Test 2 failed";

        -- Test 3: A + 1
        a <= "00000000";
        b <= "00000000";
        op <= "10";
        ci <= '1';
        wait for 10 ns;
        assert f = "00000001" and c = '0' and z = '0' and s = '0' report "Test 3 failed";

        -- Test 4: A - 1
        a <= "00000001";
        b <= "00000000";
        op <= "11";
        ci <= '1';
        wait for 10 ns;
        assert f = "00000000" and c = '0' and z = '1' and s = '0' report "Test 4 failed";

        -- Test 5: A + B with carry
        a <= "11111111";
        b <= "00000001";
        op <= "10";
        ci <= '1';
        wait for 10 ns;
        assert f = "00000001" and c = '1' and z = '0' and s = '0' report "Test 5 failed";

        -- Test 6: A - B with borrow
        a <= "00000000";
        b <= "00000001";
        op <= "11";
        ci <= '1';
        wait for 10 ns;
        assert f = "11111110" and c = '1' and z = '0' and s = '1' report "Test 6 failed";

        -- Test 7: A -> A
        a <= "01010101";
        b <= "00000001";
        op <= "11";
        ci <= '0';
        mov <= '1';
        wait for 10 ns;
        assert f = "01010101" report "Test 7 failed";
        wait for 10 ns;
        mov <= '0';

        wait;
    end process;
end BEH;